Exemplary embodiments of this invention relate to semiconductor integrated circuits each having an output circuit. More particularly, exemplary embodiments of this invention relate to a semiconductor integrated circuit having an output circuit that outputs a signal with a smaller amplitude than a power supply voltage and that consumes less electricity.
Semiconductor integrated circuits use various output circuits according to respective purposes of the integrated circuits. For example, reference 1 (JP 4-162824) and reference 2 (JP 7-249979) disclose output circuits, each of which is used in a CMOS logic integrated circuit. In each output circuit, two N-channel MOS (NMOS) transistors are connected in series between a power supply Vdd of the corresponding integrated circuit and ground (GND), and the middle point between the transistors serves as an output terminal.
Disadvantageously, when this type of output circuit is used as an output circuit for a CMOS logic integrated circuit, a high level of an output signal does not reach a power supply voltage Vdd. In other words, when the gate voltage of the NMOS transistor connected to the power supply Vdd is increased to a power supply voltage level Vdd, a voltage at the output terminal is increased to a value of Vdd−(Vt+ΔVt). Here, Vt denotes a threshold voltage in a state where the potential of the source of the NMOS transistor is equal to that of the corresponding substrate, and ΔVt denotes a variation in threshold voltage caused when the potential of the source differs from that of the substrate. For example, if the threshold voltage Vt is equal 0.7 V, then the value of Vt+ΔVt is approximately equal to 1 V.
The references 1 and 2 disclose techniques to overcome the above-mentioned disadvantage.
FIG. 4 shows an example of the output circuit disclosed in reference 1. As shown in FIG. 4, an output circuit 120 includes two output NMOS transistors 122 and 124 connected in series between a power supply Vdd and GND. The middle point between the transistors serves as an output terminal OUT. According to reference 1, a threshold voltage of the pull-up NMOS transistor 122 (directly connected to the power supply Vdd) is lower than that of the pull-down NMOS transistor 124 (directly connected to the GND). Thus, a high-level output signal can be maintained at a high level.
FIG. 5 shows an example of the output circuit disclosed in reference 2. As shown in FIG. 5, an output circuit 130 includes two output NMOS transistors 132 and 134 connected in series between a power supply Vdd and the GND. The middle point between the transistors serves as an output terminal OUT. The output circuit 130 further includes a booster circuit 138 for boosting a power supply voltage to be applied to a CMOS gate 136 that drives the NMOS transistor 132 that is directly connected to the power supply Vdd. Consequently, the gate voltage of the output transistor directly connected to the power supply is increased to a high level corresponding to the boosted voltage, so that an output level is equal to the power supply voltage.
For example, a temperature compensated crystal oscillator (TCXO), used to generate a reference frequency for communication equipment, requires an output signal with an amplitude of, e.g., approximately 1 V that is lower than a power supply voltage.
A related TCXO uses an output circuit as shown in, for example, FIG. 6. As shown in FIG. 6, an output circuit 140 is constructed such that an operating voltage applied to two output-stage NMOS transistors is lower than a power supply voltage Vdd of an integrated circuit to reduce the amplitude of an output signal. The output circuit 140 includes three NMOS transistors 146, 142, and 144 that are connected in series, in this order, between a power supply Vdd and GND. The three NMOS transistors 142, 144, and 146 have the same positive threshold voltage.
The NMOS transistors, excluding the NMOS transistor 146, are directly connected to the power supply Vdd. The first and second NMOS transistors 142 and 144 correspond to the above-mentioned output transistors 122 and 124 in the circuit shown in FIG. 4, and alternatively, correspond to the transistors 132 and 134 in the circuit shown in FIG. 5, respectively. The middle point between the first and second NMOS transistors 142 and 144 serves as an output terminal OUT. A pull-up drive circuit 154 is connected to the gate of the output transistor 142, and a pull-down drive circuit 156 is connected to the gate of the output transistor 144. Each of the pull-up drive circuit 154 and the pull-down drive circuit 156 include a plurality of CMOS gates, i.e., inverters.
On the other hand, the third NMOS transistor 146 serves as an output-stage operating voltage supply source for applying an output-stage operating voltage Vdd1 to the output transistors 142 and 144. In other words, the power supply voltage Vdd is applied to the drain of the NMOS transistor 146 and a reference voltage Vr1 is applied from a reference voltage source 150 to the gate thereof. The source of the NMOS transistor 146 provides a low voltage that is lower than the reference voltage Vr1 by an amount obtained by adding a variation ΔVt in threshold voltage, caused by the potential difference between the substrate and the source, to a threshold voltage Vt of the transist or 146 in a state where the potential of the substrate is equal to that of the source. Therefore, the voltage Vdd1 (=Vr1−(Vt+ΔVt)) is applied as an output-stage operating voltage to the output transistors 142 and 144.
The power supply voltage Vdd can also be applied as it is to the pull-up drive circuit 154. Consequently, the gate voltage of the first NMOS transistor 142, serving as a pull-up output transistor, can be increased to a higher level than the operating voltage Vdd1, that is applied to the drain of the NMOS transistor 142 in the same way as in the output circuit according to reference 2. Therefore, an output signal has an amplitude that depends on the reference voltage Vr1, the threshold voltage Vt of the third NMOS transistor 146, and the variation ΔVt in threshold voltage. The output signal is approximately equal to the output-stage operating voltage Vdd1.